[Free food] 2/17 Student Seminar: Jean Salac & Reza Jokar

Monday, February 17


JCL 390

TIPP&SEE: A Learning Strategy to Guide Students through Use → Modify Scratch Activities

Baldur: A Power-Efficient and Scalable Network Using All-Optical Switches

Student Seminar this week will be 110% more fun than usual. We have two talks (and fun scales nonlinearly)! Jean Salac and Reza Jokar will be giving practice conference presentations – abstracts are attached.

TIPP&SEE: A Learning Strategy to Guide Students through Use → Modify Scratch Activities (Jean Salac)

With the rise of Computational Thinking (CT) instruction at the elementary level,
it is imperative that elementary computing instruction support a variety of learners. A popular pedagogical approach for this age group is Use–>Modify–>Create, which introduces a concept through a more scaffolded, guided instruction before culminating in a more open-ended project for student engagement. Yet, there is little research on student learning during the Use–>Modify step, nor strategies to promote learning in this step. This paper introduces TIPP&SEE, a metacognitive learning strategy that further scaffolds student learning during this step. Results from an experimental study show statistically-significant performance gains from students
using the TIPP&SEE strategy on nearly all assessment questions of moderate and hard difficulty, suggesting its potential as an effective CS/CT learning strategy.

Baldur: A Power-Efficient and Scalable Network Using All-Optical Switches (Reza Jokar)

We present the first all-optical network, Baldur,
to enable power-efficient and high-speed communications in
future exascale computing systems. The essence of Baldur is
its ability to perform packet routing on-the-fly in the optical
domain using an emerging technology called the transistor laser
(TL), which presents interesting opportunities and challenges
at the system level. Optical packet switching readily eliminates
many inefficiencies associated with the crossings between optical and electrical domains. However, TL gates consume high
power at the current technology node, which makes TL-based
buffering and optical clock recovery impractical. Consequently,
we must adopt novel (bufferless and clock-less) architecture and
design approaches that are substantially different from those
used in current networks.

At the architecture level, we support a bufferless design
by turning to techniques that have fallen out of favor for
current networks. Baldur uses a low-radix, multi-stage network
with a simple routing algorithm that drops packets to handle congestion, and we further incorporate path multiplicity
and randomness to minimize packet drops. This design also
minimizes the number of TL gates needed in each switch.
At the logic design level, a non-conventional, length-based
data encoding scheme is used to eliminate the need for clock

We thoroughly validate and evaluate Baldur using a circuit
simulator and a network simulator. Our results show that
Baldur achieves up to 3,000X lower average latency while
consuming 3.2X-26.4X less power than various state-of-the art networks under a wide variety of traffic patterns and
real workloads, for the scale of 1,024 server nodes. Baldur
is also highly scalable, since its power per node stays relatively
constant as we increase the network size to over 1 million server
nodes, which corresponds to 14.6X-31.0X power improvements
compared to state-of-the-art networks at this scale.

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